With the progress in the semiconductor integrated circuits reaching ULSI (ultra large scale integration) level or even higher level, the integrity of the integrated circuits rises in an amazing rate. The capacity of a single semiconductor chip increases from several thousand devices to hundreds of million devices, or even billions of devices. Taking DRAM (dynamic random access memories) for example, the increasing integrity in manufacturing extends the capacity of a single chip to step from earlier 4 megabit to 16 megabit, and further to 256 megabit or even higher.
Integrated circuits devices like transistors, capacitors, and connections must be greatly narrowed accompanying with the advancement. The increasing packing density of integrated circuits generates numerous challenges to the semiconductor manufacturing process. Every element or device needs to be formed within smaller area without influencing the characteristics and functionality of the integrated circuits. The demands on high packing density, low heat generation, and low power consumption devices with good reliability and long operation life must be maintained without any degradation in the functionality. These achievements are expected to be achieved with simultaneous developments and advancements in the photography, the etching, the deposition, the ion implantation, and the thermal processing technologies, the big five aspects of semiconductor manufacturing. The present technology research focus mainly on the sub-micron and smaller semiconductor devices to manufacture highly reliable and densely arranged integrated circuits.
Transistors, or more specifically metal oxide semiconductor (MOS) transistors, are the most important and frequently employed devices in the integrated circuits. However, with the continuous narrowing of device size, the sub-micrometer scale MOS transistors have to face many risky challenges. As the MOS transistors become narrower and thinner accompanying with shorter channels, problems like the junction punchthrough, the leakage, and the contact resistance reduce the yield and the reliability of the semiconductor manufacturing. The technologies like the self-aligned silicide (salicide) and the shallow junctions are utilized in combating the undesirable effects to fabricate the densely packed devices with good yield.
The electrostatic discharge (ESD) attacking becomes a serious problem as the feature size of the MOS transistors scales down. A semiconductor device having the input/output pad connections with external circuitry and devices is subject to the problem of the ESD. The ESD is easily conducted through the input/output and the power lead connections into the internal devices and causes some problems to the semiconductor devices, especially serious ones like the gate oxide breakdown and the overheat damages. The high voltage gradient generated between the contacts and the channels from the ESD causes the gate oxide electron injection and the carrier acceleration effect in the channel. The characteristics and operations of the devices are easily damaged by the inducing effects of the ESD. A high level of ESD with several hundred volts to a few thousand volts, which is easily transferred to the pins of an IC package during handling can bring a permanent destruction to the internal devices. For preventing the devices from the ESD damaging, a built-in ESD protection circuits are connected between the input/output pads and the internal circuitry. A high level of undesired discharge conducted into the pins of an IC package is kept out by the ESD protection circuits from flowing into the devices. The discharges are guided through the ESD protection circuits to the ground and the damage to the semiconductor devices is eliminated.
Several improvements in combating the ESD problem by forming the ESD protection devices have been provided previously. For example, U.S. Pat. No. 5,559,352 to C. C. Hsue and J. Ko disclosed a method of forming an ESD protection device with reduced breakdown voltage. Their invention employed a lightly implanted region of opposite conductivity type with the source/drain regions centered under the heavier implanted source/drain region. As another example, U.S. Pat. No. 5,498,892 to J. D. Walker and S. C. Gioia disclosed a lightly doped drain ballast resistor. A field effect transistor with an improved electrostatic discharge (ESD) protection using a ballast resistor in the drain region is identified. The ballast resistor laterally distributes current along the width of the drain during an ESD pulse, which reduces local peak current density and reduces damage. But the operation speed problem with small feature size devices is still not solved. In addition, for applying most of the improvements, great efforts are needed with the variations needed in the semiconductor manufacturing circuits and the costs are raised.
In manufacturing the sub-micron feature size semiconductor devices, the salicide technology is a vital application to improve the operation speed of the ULSI/VLSI MOS devices. As mentioned in the work of P. Fornara and A. Poncet, the salicide process is one of the most efficient ways of obtaining self-aligned low resistive contacts in CMOS and BiCMOS technologies ("Modeling of Local Reduction in TiSi2 and CoSi2 Growth Near Spacers in MOS Technologies: Influence of Mechanical Stress and Main Diffusing Species", IEDM Tech. Dig., P. 73, 1996).
Unfortunately, there exists some trade-off in employing the technologies like self-aligned silicide when facing the ESD problem. The devices with the self-aligned silicided contacts show a worse ESD performance than the non-salicided devices. In general, thicker salicide has a negative effect on the ESD protection and makes the semiconductor devices to be more sensitive to the ESD voltage and damaged easily by that. The details are explored by the investigation of A. Amerasekera et al. ("Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN behavior with the ESD/EOS Performance of a 0.25 .mu.m CMOS Process.", IEDM Tech. Dig., p. 893, IEEE 1996) Their investigation presents the physical mechanisms involved in the degradation of ESD performance with shallower junctions, thicker salicides, and different epitaxial thicknesses. The ESD challenge of salicide technology with the smaller scale devices can be clearly understood by referencing their work.